1 gsps direct digital synthesizer w/ 14-bit dac preliminary technical data AD9912 rev. pr b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.co m fax: 781.461.3113 ?2007 analog devices, inc. all rights reserve d features 1 gsps internal clock speed (up to 400 mhz out directly) integrated 1 gsps 14-bit dac 48-bit frequency tuning word differential hstl comparator flexible system clock input accepts either crystal or external reference clock. on-chip low-noise pll refclk multiplier 2 spur reduction channels low jitter clock doubler for frequencies up to 750 mhz single-ended cmos comparator; frequencies < 50mhz programmable output divider for cmos output serial i/o control excellent dynamic performance software controlled power-down 64-lead lfcsp package phase noise @ 95mhz using vectron vcc6 87.5mhz oscillator: 100 hz offset: -103 dbc/hz 10 khz offset: -133 dbc/hz 1 mhz offset: -136 dbc/hz applications agile lo frequency synthesis low jitter, fine tune clock generation test and measurement equipment wireless base stations, controllers secure communications fast frequency hopping general description the AD9912 is a direct digital synthesizer (dds) featuring an integrated 14-bit dac. the AD9912 features a 48Cbit frequency tuning word (ftw) which can synthesize frequencies in step sizes no larger than 4 uhz. absolute frequency accuracy can be achieved by adjusting the dac system clock. the AD9912 also features an integrated system clock pll, which allows reference clocks as low as 25 mhz. the AD9912 operates over an industrial temperature range, spanning -40c to +85c. figure 1: basic block diagram
AD9912 preliminary technical data rev. pr b | page 2 of 3 pin configuration and fu nction descriptions pin 1 indicator AD9912 top view (not to scale) 1 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 48 38 39 40 41 42 43 44 45 46 47 33 34 35 36 37 49 57 56 55 54 53 52 51 50 58 59 60 61 62 63 64 32 24 25 26 27 28 29 30 31 23 22 21 20 19 18 17 avdd dvdd_i/o dvss dvdd s1 s2 n/c n/c n/c n/c dvss dvdd dvss dvdd dvss n/c avdd3 n/c n/c avdd n/c n/c avdd avdd avdd avdd sysclk sysclkb avdd avdd loop_filter clkmodesel dac_rset avdd3 avdd avdd3 avss avdd fdbk_in n/c fdbk_inb avss out_cmos avdd3 avdd avss out outb sclk sdo sdio io_update csb reset pwrdown n/c n/c s3 s4 avdd avss avdd3 iout ioutb figure 2: 64-lead lfcsp pin configuration table 2: pin function descriptions pin no. input/ output pin type mnemonic description 1 i power dvdd_i/o 3.3v i/o digital supply 2, 4, 6, 8 i power dvss digital ground: connect to ground 3, 5, 7 i power dvdd 1.8v digital supply 9, 10, 54, 55 i/o 3.3v cmos s1, s2, s3, s4 configurable startup strapping pins: these pins are configured under program control (see default power-up frequency options for 1 ghz system clock on page 21. after power-up, these pins become outputs. 11, 19, 23- 26, 29, 30, 36, 42, 45, 53 i power avdd analog supply: connect to a nominal 1.8v supply
preliminary technical data AD9912 rev. pr b | page 3 of 3 pr06763-0-6/07(prb) 12, 13, 15-18, 20, 21, 22, 44 n/c no connect no connect: these excess, unused pins should be left floating. 14, 37, 46, 47, 49 i power avdd3 analog supply: connect to a nominal 3.3v supply 27 i sysclk system clock input. can be lvpecl or crystal input, depending on clkmodesel pin. 28 i sysclkb complementary system clock: comple mentary signal to the input provided on pin 27 31 loop_filter system clock multiplier loop filter: when using the frequency multiplier to drive the system clock, an external loop filter must be constructed and attached to this pin. 32 i 1.8v cmos clkmodesel clock mode select. set to gnd when using a crys tal. pull up to 1.8v when using either an oscillator or external clock source. (see the sysclk inputs section for details on the use of this pin). 33, 39, 43, 52 i gnd avss analog ground: connect to ground. note: pin 43 is a ground shield connection. 34 o 1.8v hstl outb complementary hstl output: see spec table and the output drivers and multiplier section, under sub heading primary (differential) driver, for details 35 o 1.8v hstl out hstl output: see specification table and the clock drivers section 38 o 3.3v cmos out_cmos cmos output: see specificat ion table and the clock drivers section 40 i fdbk_inb complementary feedback input: in standard operating mode, this pin is connected to the filtered ioutb output . this internally bi ased input is typically ac-coupled, and when configured as such, can accept any differential signal. 41 i fdbk_in feedback input: in standard operating mode , this pin is connected to the filtered iout output 48 o dac_rset dac output current setting resistor. connect a resistor from this pin to gnd . see the dac output section. 50 o iout dac output: output signal should be filter ed and sent back on chip through fdbk_inb input 51 o ioutb complimentary dac output: output signal should be filtered and sent back on chip through fdbk_in input 56, 57 no connect no connect: these should be left floating. 58 i 3.3v cmos pwrdown power down: when this active high pin is asserted, the device goes into full power down mode. 59 i 3.3v cmos reset chip reset: when this active high pin is as serted, the chip goes into reset. note: upon power up, a 10 us reset pulse is automaticall y generated when the power supplies reach a threshold and stabilize. 60 i 3.3v cmos io_update i/o update: a logic transition from 0 to 1 on this pin transfers data from the i/o port registers to the control registers (see the write subsection of the general operation of serial control port section). 61 i 3.3v cmos csb chip select: active low. when programming a device, this pin must be held low. in systems where more than one ad9549 is pres ent this enables individual programming of each ad9549 62 o 3.3v cmos sdo serial data output: when the device is in three wire mo de, data is read on this pin 63 i/o 3.3v cmos sdio serial data input/output: when the device is in three-wire mode, data is written via this pin. in 2 wire mode, data reads and writes both occur on this pin 64 o 3.3v cmos sclk serial programming clock: data clock for serial programming.
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